1. Field of the Invention
The present invention relates generally to Phased Locked Loops (PLLs) and, more particularly, to charge correction for a PLL filter.
2. Description of the Related Art
Phased Locked Loops (PLLs) are common components utilized in a variety of applications. For example, Frequency Modulation (FM) and Amplitude Modulation (AM) modulators utilize PLLs. PLLs operate by locking onto a phase and frequency of an input signal through continual adjustment of an oscillator. The PLL oscillator can be current or voltage driven. Typically, though, the PLL oscillator is a Voltage Controlled Oscillator (VCO).
Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional PLL. A conventional PLL comprises a Phase-Frequency Detector (PFD) 102, a charge pump 104, a Low Pass Filter (LPF) 106, a VCO 108, and a frequency divider 110.
The illustration of the components of the PLL, though, do not necessarily lend to a complete explanation. The LPF 106 further comprises a capacitor 116 and a resistor 118 which operated on the principle of capacitive impedance where impedance of a capacitor is inversely proportional to the signal frequency. Also, the charge pump 104 further comprises a first current source 105, a second current source 107, a first switch 112, and a second switch 114.
The PLL operates by maintaining charge on the first capacitor 116 of the LPF 106. A reference signal or input signal is input into the PFD 102 through a first node 122 along with feedback from the frequency divider 110 through a second node 132. Based on the comparison between the inputted signals, the PFD 102 either activates the first switch 112 of the charge pump 104 through a third node 124 or activates the second switch 114 of the charge pump 104 through a fourth node 126. By activating the first switch 112, the charge is added to the capacitor 116 of the LPF 106 through a fifth node 128. By activating the second switch 114, charge is removed from the capacitor 116 of the LPF 106 through the fifth node 128.
The active pulling down and pulling up the charge of the capacitor effectively changes the voltage of the LPF 106. The voltage of the LPF 106 is then used to control the voltage of the frequency and phase of the VCO 108. The voltage of the LPF 106 is maintained at the fifth node 128, which is input into the VCO 108. The VCO 108 then outputs an output signal through a sixth node 130 that has its phase and frequency synchronized with the input signal. The output signal from the VCO 108 is input into the frequency divider 110. Also, the output signal of VCO 108 is used in a variety of circuits to perform a variety of tasks.
With a conventional PLL 100 of FIG. 1, though, there are some disadvantages. Due to the advancement of Complimentary Metal-Oxide on a Semiconductor (CMOS) technology, the resulting thickness of the dielectric of the capacitor 116 of FIG. 1 has become increasingly smaller. As a result of decreasing thickness of the dielectric, there has been an increase in the leakage current across the capacitor 116 of FIG. 1. The PLL, then cannot maintain, the proper voltage for the VCO 108 of FIG. 1 resulting in drift of the locked in phase and frequency.
Therefore, there is a need for a method and/or apparatus for correction of leakage voltage in a PLL that addresses at least some of the problems associated with conventional methods and apparatuses for PLLs.